1. Field of Invention
The present invention relates to a method of chip manufacturing. More particularly, the present invention relates to a method chip testing and packaging during the process of chip manufacturing.
2. Description of Related Art
As electronic devices are becoming smaller and slimmer, IC chip manufacturing process is becoming more complex. FIG. 1 shows a flow chart of the conventional manufacturing process essentially consists of a design stage 101, a simulation stage 102, a foundry stage 103, a DC/RF probing stage 104, a cutting stage 105, a packaging/coating stage 106 and a final testing stage 107. Difficulties arise when the DC/RF probing stage 104 is not carried out in an easy, accurate and cost efficient manner. The current DC/RF probing stage 104 is done before cutting to ensure only the good dies are packaged. The primary purpose of such probing is to save packaging costs. Probes move to designated pads by an X-Y coordinate controlling scheme and probes each pad on the chip individually. The DC/RF probing stage 104, especially RF probing, lacks accuracy, as the result curves will shift over time creating high error rates in measurements. Even if accurate measurements can be obtained, the results may not be a good representation of the chip performance since packaging will introduce additional parasitics degrading the performance in the RF domain. This creates many problems in the design cycle since the designer will not discover many design flaws until after packaging. Re-designing the IC after packaging is a time consuming and painful process. The re-design cycle may take months and with the current DC/RF probing stage 104, it is hard for the simulation results to be a close estimation of the actual performance before packaging. Furthermore, the cost of DC/RF probing is very high. It may take thousands of probes to perform the DC probing test and the cost of RF probe is in the range of hundreds of dollars each. RF probes are also very fragile and wear off relatively fast. They also may damage the pads. Since a typical RF wafer yield is in between 50% and 70%, we cannot simply drop the wafer probing test to save the manufacturing cost.
As the trend also demands faster processing speed and ubiquitous communication, thus the IC design will require higher frequency and integrated multiple standards in a single chip, and inevitably becomes more difficult to verify due to increasing complexity and interferences. As a result, it will have a longer IC design cycle and lower yield rate.
For the forgoing reasons, there is a need for a new method of chip manufacturing. More particularly, a new method of testing and packaging to simplify and cost down the design cycle, especially at the DC/RF probing stage 104.